An FPGA implementation of a long short-Term memory neural network

dc.contributor.author João Canas Ferreira en
dc.contributor.author Fonseca,J en
dc.date.accessioned 2018-01-05T16:07:44Z
dc.date.available 2018-01-05T16:07:44Z
dc.date.issued 2017 en
dc.description.abstract Our work proposes a hardware architecture for a Long Short-Term Memory (LSTM) Neural Network, aiming to outperform software implementations, by exploiting its inherent parallelism. The main design decisions are presented, along with the proposed network architecture. A description of the main building blocks of the network is also presented. The network is synthesized for various sizes and platforms, and the performance results are presented and analyzed. Our synthesized network achieves a 251 times speed-up over a custom-built software network, running on an i7-3770k Desktop computer, proving the benefits of parallel computation for this kind of network. © 2016 IEEE. en
dc.identifier.uri http://repositorio.inesctec.pt/handle/123456789/5540
dc.identifier.uri http://dx.doi.org/10.1109/reconfig.2016.7857151 en
dc.language eng en
dc.relation 473 en
dc.rights info:eu-repo/semantics/openAccess en
dc.title An FPGA implementation of a long short-Term memory neural network en
dc.type conferenceObject en
dc.type Publication en
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