FPGA-based High-Level Design Strategies to Accelerate a 3D Path Planning Algorithm
FPGA-based High-Level Design Strategies to Accelerate a 3D Path Planning Algorithm
dc.contributor.author | João Paiva Cardoso | en |
dc.contributor.author | João Teixeira | en |
dc.contributor.author | Ali Azarian | en |
dc.contributor.author | José Carlos Alves | en |
dc.date.accessioned | 2017-11-16T14:01:32Z | |
dc.date.available | 2017-11-16T14:01:32Z | |
dc.date.issued | 2012 | en |
dc.description.abstract | This work presents the results of applying diverse high-level optimization strategies for FPGA hardware acceleration of a computational intensive application, using a commercial C to RTL high-level synthesis tool (CatapultC). The application was provided by an industry partner and is the critical part of a real-time path planning algorithm for unmanned aerial vehicles operating on three dimensional environments with dynamic obstacles. | en |
dc.identifier.uri | http://repositorio.inesctec.pt/handle/123456789/2710 | |
dc.language | eng | en |
dc.relation | 258 | en |
dc.relation | 258 | en |
dc.relation | 5550 | en |
dc.relation | 5550 | en |
dc.rights | info:eu-repo/semantics/openAccess | en |
dc.title | FPGA-based High-Level Design Strategies to Accelerate a 3D Path Planning Algorithm | en |
dc.type | conferenceObject | en |
dc.type | Publication | en |