FPGA-based High-Level Design Strategies to Accelerate a 3D Path Planning Algorithm
FPGA-based High-Level Design Strategies to Accelerate a 3D Path Planning Algorithm
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Date
2012
Authors
João Paiva Cardoso
João Teixeira
Ali Azarian
José Carlos Alves
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Abstract
This work presents the results of applying diverse high-level optimization strategies for FPGA
hardware acceleration of a computational intensive application, using a commercial C to RTL
high-level synthesis tool (CatapultC). The application was provided by an industry partner and
is the critical part of a real-time path planning algorithm for unmanned aerial vehicles
operating on three dimensional environments with dynamic obstacles.