CTM - Indexed Articles in Journals

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Browsing CTM - Indexed Articles in Journals by Author "5802"
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    BacalhauNet: A tiny CNN for lightning-fast modulation classification
    ( 2022) Jose Rosa ; Daniel Granhao ; Guilherme Carvalho ; Tiago Gon?alves ; Monica Figueiredo ; Luis Conde Bento ; Nuno Miguel Paulino ; Luis M. Pessoa ; 5802
    Deep learning methods have been shown to be competitive solutions for modulation classification tasks, but suffer from being computationally expensive, limiting their use on embedded devices. We propose a new deep neural network architecture which employs known structures, depth-wise separable convolution and residual connections, as well as a compression methodology, which combined lead to a tiny and fast algorithm for modulation classification. Our compressed model won the first place in ITU's AI/ML in 5G Challenge 2021, achieving 61.73? compression over the challenge baseline and being over 2.6? better than the second best submission. The source code of this work is publicly available at github.com/ITU-AI- ML-in-5G-Challenge/ITU-ML5G-PS-007-BacalhauNet.
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    Improving performance and energy consumption in embedded systems via binary acceleration: A survey
    ( 2020) Nuno Miguel Paulino ; João Canas Ferreira ; João Paiva Cardoso ; 473 ; 5550 ; 5802
    The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. © 2020 Association for Computing Machinery.
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    Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes
    ( 2022) Nuno Miguel Paulino ; Luís Manuel Pessoa ; Branquinho,A ; Almeida,R ; Ferreira,I ; 5802 ; 4760