Browsing by Author João Canas Ferreira

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Issue DateTitleAuthor(s)
2017MICPRO DSD 2015 special issueJoão Canas Ferreira; Kitsos,P
2009Non-Rectangular Reconfigurable Cores for Systems-on-ChipPedro Alves; João Canas Ferreira
2010The Performance Impact when Optimizing Mapping Algorithms for an FPGA-based Mobile RobotMaria João Cardoso; Luís Manuel Reis; João Canas Ferreira
2016A Precise and Hardware-Efficient Time Synchronization Method for Wearable Wired NetworksDerogarian,F; João Canas Ferreira; Vítor Grade Tavares
2011Proceedings of the 26th Conference on Design of Circuits and Integrated SystemsJosé Machado da Silva; Sylvie Renaud; João Canas Ferreira
2010Real-Time Stereo Matching on FPGACarlos Resende; João Canas Ferreira
2015A Reconfigurable Architecture for Binary Acceleration of Loops with Memory AccessesPaulino,N; João Canas Ferreira; João Paiva Cardoso
2016Reconfigurable FPGA-based FFT processor for cognitive radio applicationsFerreira,ML; Amin Barahimi; João Canas Ferreira
2015Reconfigurable NC-OFDM Processor for 5G CommunicationsMário Lopes Ferreira; João Canas Ferreira
2013Register transfer level workflow for application and evaluation of soft error mitigation techniquesSousa,F; Anghinolfi,F; João Canas Ferreira
2011A Routing Protocol for WSN Based on the Implementation of Source Routing for Minimum Cost Forwarding MethodVítor Grade Tavares; Fardin Derogarian Miyandoab; João Canas Ferreira
2010Run-time Generation of Partial Configurations for Arithmetic ExpressionsJoão Canas Ferreira; Miguel L. Silva
2012Run-time Generation of Partial FPGA ConfigurationsMiguel L. Silva; João Canas Ferreira
2012Run-time generation of partial FPGA configurations for subword operationsJoão Canas Ferreira; Miguel Silva
2010Run-time Generation of Partial FPGA Configurations for Subword OperationsMiguel Silva; João Canas Ferreira
2012A Scalable Array for Cellular Genetic Algorithms: TSP as Case StudyJoão Canas Ferreira; Pedro Manuel Santos; José Carlos Alves
2016Scalable hardware architecture for disparity map computation and object location in real-timeSantos,PM; João Canas Ferreira; José Silva Matos
2016A small fully digital open-loop clock and data recovery circuit for wired BANsDerogarian,F; João Canas Ferreira; Vítor Grade Tavares
2013Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011)José Machado da Silva; Renaud,S; João Canas Ferreira
2014A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable NetworksDerogarian,F; João Canas Ferreira; Vítor Grade Tavares