Skip navigation
Browse
Communities
& Collections
Browse Items by:
Issue Date
Author
Title
Subject
Type
Location
Contributor
Help
Language
português
English
Sign on to:
My DSpace
Receive email
updates
Edit Profile
INESCTEC
Browsing by Author João Paiva Cardoso
Jump to:
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
or enter first few letters:
Sort by:
title
issue date
submit date
In order:
Ascending
Descending
Results/Page
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Authors/Record:
All
1
5
10
15
20
25
30
35
40
45
50
Showing results 1 to 20 of 22
next >
Issue Date
Title
Author(s)
2016
The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems
Silvano,C
;
Agosta,G
;
Cherubin,S
;
Gadioli,D
;
Palermo,G
;
Bartolini,A
;
Benini,L
;
Martinovic,J
;
Palkovic,M
;
Slaninová,K
;
João Bispo
;
João Paiva Cardoso
;
Rui Maranhão
;
Pinto,P
;
Cavazzoni,C
;
Sanna,N
;
Beccari,AR
;
Cmar,R
;
Rohou,E
2013
Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
Paulino,N
;
João Canas Ferreira
;
João Paiva Cardoso
2016
AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems: the ANTAREX Approach
Silvano,C
;
Agosta,G
;
Bartolini,A
;
Beccari,AR
;
Benini,L
;
João Bispo
;
Cmar,R
;
João Paiva Cardoso
;
Cavazzoni,C
;
Martinovic,J
;
Palermo,G
;
Palkovic,M
;
Pinto,P
;
Rohou,E
;
Sanna,N
;
Slaninova,K
2015
C and OpenCL Generation from MATLAB
João Bispo
;
Luís Cubal Reis
;
João Paiva Cardoso
2017
Compiler Techniques for Efficient MATLAB to OpenCL Code Generation
Luís Cubal Reis
;
João Bispo
;
João Paiva Cardoso
2017
Expressing and Applying C++ Code Transformations for the HDF5 API Through a DSL
Golasowski,M
;
João Bispo
;
Martinovic,J
;
Slaninová,K
;
João Paiva Cardoso
2012
FPGA-based High-Level Design Strategies to Accelerate a 3D Path Planning Algorithm
João Paiva Cardoso
;
João Teixeira
;
Ali Azarian
;
José Carlos Alves
2017
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces
Nuno Miguel Paulino
;
João Canas Ferreira
;
João Paiva Cardoso
2012
Hardware acceleration of a Stereo Navigation application with high-level C to HW synthesis
José Carlos Alves
;
João Paiva Cardoso
;
Zlatko Petrov
;
João Vilela Teixeira
2013
Hardware pipelining of repetitive patterns in processor instruction traces
João Bispo
;
João Paiva Cardoso
;
Monteiro,J
2017
LARA as a language-independent aspect-oriented programming approach
Pinto,P
;
Carvalho,T
;
João Bispo
;
João Paiva Cardoso
2013
The MATISSE MATLAB Compiler
João Bispo
;
Pinto,P
;
Ricardo Ferreira Nobre
;
Carvalho,T
;
João Paiva Cardoso
;
Pedro Diniz
2017
A MATLAB subset to C compiler targeting embedded systems
João Bispo
;
João Paiva Cardoso
2014
Multi-target c code generation from MATLAB
João Bispo
;
Luís Cubal Reis
;
João Paiva Cardoso
2015
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
Paulino,N
;
João Canas Ferreira
;
João Paiva Cardoso
2012
Specifying Compiler Strategies for FPGA-based Systems
José Carlos Alves
;
João Paiva Cardoso
;
Nome Apelido
2016
SSA-based MATLAB-to-C compilation and optimization
Luís Cubal Reis
;
João Bispo
;
João Paiva Cardoso
2015
Techniques for efficient MATLAB-to-C compilation
João Bispo
;
Luís Cubal Reis
;
João Paiva Cardoso
2014
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
Paulino,N
;
João Canas Ferreira
;
João Paiva Cardoso
2015
Transparent acceleration of program execution using reconfigurable hardware
Nuno Miguel Paulino
;
João Canas Ferreira
;
João Bispo
;
João Paiva Cardoso