Design of a Current-Mode Class-D Power Amplifier in RF-CMOS

Abstract

The present paper addresses the implementation of a radio-frequency power amplifier operating in current-mode class-D. In particular, this paper focuses the technical issues concerning the design of a fully-integrated version of the amplifier in a RF-CMOS technology. It is demonstrated that the parasitic series resistance of an integrated load inductor has great impact in the drain efficiency value. In order to compensate for this effect, the reduction of the load network QL has been adopted. A RF-CMCD power amplifier has been designed in 90-nm CMOS including all the inductors on-chip. Simulation results demonstrate 76% drain efficiency, for up to 16-dBm output power at 2.45-GHz operation frequency.