Analog circuits with high-gain topologies using a-GIZO TFTs on glass
Analog circuits with high-gain topologies using a-GIZO TFTs on glass
dc.contributor.author | Bahubalindruni,PG | en |
dc.contributor.author | Silva,B | en |
dc.contributor.author | Vítor Grade Tavares | en |
dc.contributor.author | Barquinha,P | en |
dc.contributor.author | Cardoso,N | en |
dc.contributor.author | Guedes De Oliveira,P | en |
dc.contributor.author | Martins,R | en |
dc.contributor.author | Fortunato,E | en |
dc.date.accessioned | 2018-01-16T16:35:21Z | |
dc.date.available | 2018-01-16T16:35:21Z | |
dc.date.issued | 2015 | en |
dc.description.abstract | This paper presents analog building blocks that find potential applications in display panels. A buffer (source-follower), subtractor, adder, and high-gain amplifier, employing only n-type enhancement amorphous gallium-indium-zinc-oxide thin-film transistors (a-GIZO TFTs), were designed, simulated, fabricated, and characterized. Circuit simulations were carried out using a neural model developed in-house from the measured characteristics of the transistors. The adder-subtractor circuit presents a power consumption of 0.26 mW, and the amplifier presents a gain of 34 dB and a power consumption of 0.576 mW, with a load of 10 MO16 pF. To the authors' knowledge, this is the highest gain reported so far for a single-stage amplifier with a-GIZO TFT technology. © 2015 IEEE. | en |
dc.identifier.uri | http://repositorio.inesctec.pt/handle/123456789/6457 | |
dc.identifier.uri | http://dx.doi.org/10.1109/jdt.2014.2378058 | en |
dc.language | eng | en |
dc.relation | 2152 | en |
dc.rights | info:eu-repo/semantics/openAccess | en |
dc.title | Analog circuits with high-gain topologies using a-GIZO TFTs on glass | en |
dc.type | article | en |
dc.type | Publication | en |
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