Specifying Compiler Strategies for FPGA-based Systems
Specifying Compiler Strategies for FPGA-based Systems
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Date
2012
Authors
José Carlos Alves
João Paiva Cardoso
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Abstract
The development of applications for highperformance
Field Programmable Gate Array (FPGA) based
embedded systems is a long and error-prone process.
Typically, developers need to be deeply involved in all the
stages of the translation and optimization of an application
described in a high-level programming language to a lowerlevel
design description to ensure the solution meets the
required functionality and performance. This paper describes
the use of a novel aspect-oriented hardware/software design
approach for FPGA-based embedded platforms. The designflow
uses LARA, a domain-specific aspect-oriented
programming language designed to capture high-level
specifications of compilation and mapping strategies,
including sequences of data/computation transformations and
optimizations. With LARA, developers are able to guide a
design-flow to partition and map an application between
hardware and software components. We illustrate the use of
LARA on two complex real-life applications using high-