Hardware acceleration of a Stereo Navigation application with high-level C to HW synthesis
Hardware acceleration of a Stereo Navigation application with high-level C to HW synthesis
No Thumbnail Available
Date
2012
Authors
José Carlos Alves
João Paiva Cardoso
Zlatko Petrov
João Vilela Teixeira
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
Hardware acceleration is a well established solution to
accelerate computational intensive applications, in particular
for embedded applications based on performance
constrained processors. However, the effort for designing
hardware architectures capable of effectively improving the
execution time of a software application, makes this approach
almost exclusively affordable to experienced hardware
designers. This paper describes a case study on how
effective an automated high-level synthesis tool can be for
the creation of RTL architectures from untimed software
algorithms. The high-level synthesis tool CatapultC from
Mentor Graphics was used for translating the most time
consuming sections of an image based navigation application.
The lack of support of floating point arithmetic was
identified as a major limitation of this tool, when synthesizing
C code that really requires floating point computations [...].