Hardware pipelining of repetitive patterns in processor instruction traces
Hardware pipelining of repetitive patterns in processor instruction traces
dc.contributor.author | João Bispo | en |
dc.contributor.author | João Paiva Cardoso | en |
dc.contributor.author | Monteiro,J | en |
dc.date.accessioned | 2018-01-16T15:18:41Z | |
dc.date.available | 2018-01-16T15:18:41Z | |
dc.date.issued | 2013 | en |
dc.description.abstract | Dynamic partitioning is a promising technique where computations are transparently moved from a General Purpose Processor (GPP) to a coprocessor during application execution. To be effective, the mapping of computations to the coprocessor needs to consider aggressive optimizations. One of the mapping optimizations is loop pipelining, a technique extensively studied and known to allow substantial performance improvements. This paper describes a technique for pipelining Megablocks, a type of runtime loop developed for dynamic partitioning. The technique transforms the body of Mega-blocks into an acyclic dataflow graph which can be fully pipe-lined and is based on the atomic execution of loop iterations. For a set of 9 benchmarks without memory operations, we generated pipelined hardware versions of the loops and esti-mate that the presented loop pipelining technique increases the average speedup of non-pipelined coprocessor accelerated designs from 1.6× to 2.2×. For a larger set of 61 benchmarks which include memory operations, we estimate through simulation a speedup increase from 2.5× to 5.6× with this technique. | en |
dc.identifier.uri | http://repositorio.inesctec.pt/handle/123456789/6393 | |
dc.language | eng | en |
dc.relation | 6527 | en |
dc.relation | 5550 | en |
dc.rights | info:eu-repo/semantics/openAccess | en |
dc.title | Hardware pipelining of repetitive patterns in processor instruction traces | en |
dc.type | article | en |
dc.type | Publication | en |
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