Please use this identifier to cite or link to this item: http://repositorio.inesctec.pt/handle/123456789/2710
Title: FPGA-based High-Level Design Strategies to Accelerate a 3D Path Planning Algorithm
Authors: João Paiva Cardoso
João Teixeira
Ali Azarian
José Carlos Alves
Issue Date: 2012
Abstract: This work presents the results of applying diverse high-level optimization strategies for FPGA hardware acceleration of a computational intensive application, using a commercial C to RTL high-level synthesis tool (CatapultC). The application was provided by an industry partner and is the critical part of a real-time path planning algorithm for unmanned aerial vehicles operating on three dimensional environments with dynamic obstacles.
URI: http://repositorio.inesctec.pt/handle/123456789/2710
metadata.dc.type: conferenceObject
Publication
Appears in Collections:CSIG - Articles in International Conferences

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