Please use this identifier to cite or link to this item: http://repositorio.inesctec.pt/handle/123456789/5562
Title: Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
Authors: Paulino,N
João Canas Ferreira
João Paiva Cardoso
Issue Date: 2014
Abstract: This paper presents a binary acceleration approach based on extending a General Purpose Processor (GPP) with a Reconfigurable Processing Unit (RPU), both sharing an external data memory. In this approach repeating sequences of GPP instructions are migrated to the RPU. The RPU resources are selected and organized off-line using execution trace information. The RPU core is composed of Functional Units (FUs) that correspond to single CPU instructions. The FUs are arranged in stages of mutually independent operations. The RPU can enable several stages in tandem, depending on the data dependencies. External data memory accesses are handled by a configurable dual-port cache. A prototype implementation of the architecture on a Spartan-6 FPGA was validated with 12 benchmarks and achieved an overall geometric mean speedup of 1.91x.
URI: http://repositorio.inesctec.pt/handle/123456789/5562
http://dx.doi.org/10.1109/ispa.2014.29
metadata.dc.type: conferenceObject
Publication
Appears in Collections:CSIG - Articles in International Conferences
CTM - Articles in International Conferences

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