Please use this identifier to cite or link to this item: http://repositorio.inesctec.pt/handle/123456789/6465
Title: a-GIZO TFT neural modeling, circuit simulation and validation
Authors: Bahubalindruni,PG
Vítor Grade Tavares
Barquinha,P
Manuel Cândido Santos
Cardoso,N
de Oliveira,PG
Martins,R
Fortunato,E
Issue Date: 2015
Abstract: Development time and accuracy are measures that need to be taken into account when devising device models for a new technology. If complex circuits need to be designed immediately, then it is very important to reduce the time taken to realize the model. Solely based on data measurements, artificial neural networks (ANNs) modeling methodologies are capable of capturing small and large signal behavior of the transistor, with good accuracy, thus becoming excellent alternatives to more strenuous modeling approaches, such as physical and semi-empirical. This paper then addresses a static modeling methodology for amorphous Gallium-Indium-Zinc-Oxide - Thin Film Transistor (a-GIZO TFT), with different ANNs, namely: multilayer perceptron (MLP), radial basis functions (RBF) and least squares-support vector machine (LS-SVM). The modeling performance is validated by comparing the model outcome with measured data extracted from a real device. In case of a single transistor modeling and under the same training conditions, all the ANN approaches revealed a very good level of accuracy for large- and small-signal parameters (g(m) and g(d)), both in linear and saturation regions. However, in comparison to RBF and LS-SVM, the MLP achieves a very acceptable degree of accuracy with lesser complexity. The impact on simulation time is strongly related with model complexity, revealing that MLP is the most suitable approach for circuit simulations among the three ANNs. Accordingly, MLP is then extended for multiple TFTs with different aspect ratios and the network implemented in Verilog-A to be used with electric simulators. Further, a simple circuit (inverter) is simulated from the developed model and then the simulation outcome is validated with the fabricated circuit response.
URI: http://repositorio.inesctec.pt/handle/123456789/6465
http://dx.doi.org/10.1016/j.sse.2014.11.009
metadata.dc.type: article
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